About program

CacheBurst32 is a diagnosis and benchmarking utility designed to measure bandwidth and latency of computer memory and cache subsystems.

A latest version of program can be found on the web page http://user.rol.ru/~dxover/cburst

Copyright © 2002 Vladimir Afanasiev and Sergey Romanov.


Disclaimer

Cache Burst 32 is Freeware and provided As is without warranty of any kind. There is no guarantee that obtained results will be accurate. Authors are not liable for losses incurred by use of this software and bear no responsibility, neither direct nor implied, for any damaged user hardware or corrupted data. We strongly recommend looking through Requirements page before using this software. You are free to use it by yourself and to distribute it in original condition (with this manual).


Requirements

  • x86 compatible central processor supporting CPUID and RDTSC instructions *.
  • Microsoft Windows 95/98/Me/NT/2000/XP
  • At least 36 Mbytes free physical RAM.

    * CPU with SSE or MMX instruction set recommended.

You must close all active and background applications before running tests otherwise their operation will be blocked. That may lead to failures in some programs and damaging your data. For accurate results it is recommended to run Cache Burst 32 right after booting into Windows.


Buttons

 Start
Start button performs check for available memory amount and launches benchmark. Diagram will be drawn as selected tests run.
Report
Report button creates a HTML report in Cache Burst 32 directory. Report for Memory Walk differs from one for other tests. Also diagram data is transferred to a comma-delimited text file (.CSV format) so it further can be reproduced in Microsoft Excel.
Exit
Exit button closes a program. You can not interrupt benchmark until it ends so you really need it may try to shutdown the task with Task Manager.


Menu commands

 File
Actions this menu completely duplicate an functions of buttons.
Settings
Action Colors this menu allows customizing diagram palette.
Help
Actions this menu allows viewing help and version information.


Adjustments

Read, Write, Copy, MMX Read/Write/Copy, SSE Read/Write/Copy and Read Latency checkboxes are used to activate corresponding speed measurements. When CPU does not support MMX or SSE instructions appropriate checkboxes will be grayed. Multiple checked positions are allowed except Memory Walk test which must be run separate.

Start/End Block Size

Start/End block size dropdown list define minimal and maximal block size for bandwidth and latency tests.
Read Latency Step
Read Latency Step is used to select a desired step for latency testing.
Memory Walk Start Step
Memory Walk Start Step dropdown list define a starting step for Memory Walk test.
Copy to Itself
Copy to Itself checkbox is available when one of the copy tests selected and makes copied data to be overwritten by it self. In that case memory content is not actually modified. When it is not set, data is copied to a position next to the test block size.
Log Y Axis
Log Y Axis checkbox makes Y axis of the diagram logarithmic with a power of two.
4x Iteration
4x Iteration checkbox quadruple the number of each test passes for better precision. This also causes benchmark to be four times longer.


Bandwidth tests

Bandwidth in Cache Burst 32 is measured as read, write and copy speeds for either 32-bit, 64-bit (MMX) or 128-bit (SSE) accesses. Algorithms are optimized for small dataset sizes to better reflect cache bandwidth. That is why other programs may indicate more memory bandwidth compared to Cache Burst 32.
Copy to itself option because of 100% cache hit for write operations allows to test cache and memory read-around-write capability. This way increases cache utilization and is much easier test for memory subsystem, which translates into higher numbers and lower test time.


Latency tests

Latency in Cache Burst 32 is a load to use latency. In other words it is time in cycles it takes for CPU to read a small amount of random data. Read latency draws cache and memory latencies for specified step while Memory Walk test cycles through all steps and draws latency of memory read accesses. Memory Walk test will freeze time to time and take several minutes to accomplish. Such behavior is by design.
When step is less than cache line size we measure time to get a critical word, so you must set the step equal or greater then cache line size to measure second level cache and memory latency.


Known issues

1. MMX/SSE memory read speed may fluctuate on some computers. Change End block size to avoid this.

2. L2 cache latency is 4 cycles higher than it should be on Athlon-Palomino and Duron-Morgan processors when step is equal to cache line size. Set Read Latency Step to 128 bytes to get correct results.


FAQ

While no questions.


What's new?

 Version 0.90.70
- First version released to public.
Version 0.90.91
- Added detection Memory Peak Bandwidth.
- Added more CPU detection.
- Some additions, updates and bugs fixed.